1. Field of the Invention
This invention relates to a method of planarizing an integrated circuit device using a spin-on-glass composition. More particularly, this invention relates to a method of planarizing a submicron integrated circuit device using a spin-on-glass layer which is thermally cured and ion implanted throughout the entire thickness of the spin-on-glass layer, thus imparting to the spin-on-glass layer the characteristic of not being susceptible to sorption and outgassing of moisture.
2. Description of Related Art
Conventional processes used in production of integrated circuit devices include metallization processes which produce conductive pathways to connect various circuit elements, and dielectric deposition processes which form insulating layers between adjoining or overlapping conductive metal layers. In practice, such conventional processes will typically first involve the deposition of a blanket metal layer which is patterned by lithographic and etching techniques. A conformal dielectric layer, which is typically silicon oxide material, is then formed over the patterned metal layer.
These conventional metallization and dielectric processes are adequate for simple device structures and dimensions. However, as device structures and dimensions become more complex and intricate the conventional metallization and dielectric processes often approach their limits of utility. These limits can easily be exceeded in situations where a device structure has substantially differing feature heights. Such feature height differences may be encountered in integrated circuit devices having multiple or overlapping metallization schemes, which might include, for example, memory word lines and like structures in memory products.
The occurrence of substantially differing feature heights in a semiconductor device creates a dilemma in the choice of thickness of a conventional conformal dielectric layer for use in that device. In general, a thick conformal dielectric layer will provide the most complete planarization, thus ensuring adequate coverage of all features. Unfortunately, however, thick conformal dielectric layers are susceptible to void formation during the conformal coating process. In contrast, thin conformal dielectric layers are much less likely to form voids. However, they suffer from a separate set of deficiencies. These deficiencies include: (1) an inability of a thin conformal dielectric layer to form an adequately planar surface upon which additional device elements may be formed, and (2) an inability of a thin conformal dielectric layer to adequately protect an underlying metal layer.
These inherent limits in the use of conventional conformally coated dielectric layers in advanced semiconductor device structures have spurned the development of alternate methods and materials designed to provide void free planar dielectric layers. Spin-on-glass materials represent a class of such alternate materials which have been used to provide void free planar dielectric layers in advanced integrated circuits. Two common members of the class of spin-on-glass materials are: (1) the inorganic silicate type spin-on-glass, and (2) the organic functional siloxane type spin-on-glass.
Both silicate and siloxane spin-on-glass materials are usually provided as dilute solutions in appropriate solvents. To form a spin-on-glass layer, a spin-on-glass solution is deposited onto a semiconductor wafer surface and the wafer is spun at a high speed to produce a uniform layer of material from which much of the solvent has evaporated. Further removal of solvent can be accomplished through mild heating or vacuum treatment of the wafer surface. Multiple layers of spin-on-glass material may be formed upon an initial layer by repeated coating applications.
In order to achieve optimal characteristics, layers composed of spin-on-glass materials must be thoroughly cured. Curing is usually done at temperatures of between 425 C. to 450 C. for a time period of up to one hour. During the curing process significant chemical and physical changes occur in both silicate and siloxane type spin-on-glass layers.
In its most common application for planarization of a semiconductor surface, a spin-on-glass material is applied as the middle layer of a three layer sandwich dielectric composition. In this sandwich layer, a conformal oxide is first applied to the semiconductor surface. A spin-on-glass composition is then spin coated onto the conformal oxide and cured. Finally a second oxide layer is deposited upon the cured spin-on-glass layer.
Once a spin-on-glass sandwich layer has been produced on a semiconductor surface, vias may be lithographically etched through the layer for the purpose of connecting to an underlying metal layer. Conventional lithographic techniques may be used to etch vias through spin-on-glass sandwich layers. A common process step included in the conventional lithographic via etch process is the removal of the photoresist etch mask by an oxygen plasma ash process.
Unfortunately, the oxygen plasma ash process for via photoresist etch mask removal causes oxide damage to form on the exposed spin-on-glass layer within the etched via. This is consistent with the observations of Rutherfold, et al., Proc. of the IEEE 141 (1993), who have shown that oxygen plasmas cause an increase in Si-OH (silicon-hydroxyl) bonding and a decrease in Si-C (silicon-carbon) bonding in siloxane spin-on-glass layers. In turn, the oxide damage caused by the oxygen plasma has an affinity to adsorb moisture when exposed to ambient air. This adsorbed moisture will desorb from the spin-on-glass surface oxide during any subsequent vacuum processing. In situations where the subsequent vacuum processing involves metal deposition into spin-on-glass sandwich layer vias whose sidewalls have adsorbed moisture due to oxidation, problems are often encountered with moisture outgassing or high via resistance due to moisture induced via metal oxidation.
One method of addressing high via metal resistance caused by spin-on-glass surface moisture desorption is to provide an additional etch-back process step to remove surface moisture from the oxidized spin-on-glass in via sidewalls prior to deposition of metal into those vias. Although this method is usually successful it also has some disadvantages. First, this method increases semiconductor processing time. Second, this method may not provide comparable etch rates for the spin-on-glass layer and the conformal oxide layers. Variations in etch rates between those materials will cause undercut or overcut of the spin-on-glass sandwich structure providing opportunities for voids or other semiconductor reliability defects.
Several patents have described methods and problems associated with spin-on-glass planarization processes. For example, U.S. Pat. No. 5,003,062 to Yen describes a sandwich process in which the spin-on-glass material may be either silicate or siloxane. A vacuum degassing step is used within that process. U.S. Pat. No. 4,775,550 to Chu, et al. describes a spin-on-glass process having a very thick first insulating layer, on the order of 8,000 to 10,000 Angstroms. Conformal insulator thicknesses in this range often experience voids. The aforementioned patent to Chu et al., as well as U.S. Pat. No. 4,676,867 to Elkins et al and U.S. Pat. No. 4,885,262 to Ting et al. each show spin-on-glass etchback processes with the use of a spin-on-glass sandwich dielectric.
In addition, U.S. Pat. No. 5,192,697 to Leong describes an ion implantation method which may be used in place of the conventional thermal method for curing of spin-on-glass layers. "Modification Effects in Ion-Implanted SiO2 Spin on Glass" by Moriya et al, 140 J. Electrochem. Soc. 1442 (1993), describes physical effects caused by ion implanting into silicate and siloxane spin-on-glass layers formed on silicon wafers.
Finally, a recent U.S. patent application (Ser. No. 08/224701, filed 8 Apr. 1994) by Liu, et al. from this laboratory describes an ion implant process for improving semiconductor process yields of devices which contain spin-on-glass sandwich layers. Both the Moriya et al. article and the patent application describe ion implantation processes which are similar to the processes of the present invention. However, both of those publications describe ion implant processes employing relatively high implant dosages and low implant energies where the implanted ions are limited to Arsenic, Silicon and Phosphorus.